1. Field of the Invention
This invention relates to electronic circuits, and in particular to a voltage non-binary encoding and decoding circuit capable of transmitting and receiving multiple-level voltage signals on a single physical I/O pin.
2. Description of the Prior Art
Multiplexing circuits for encoding and decoding multiple binary signals are well known. Voltage-based multiplexing is capable of encoding N bits of data into one or more discrete voltage levels during a set time period. Conventional voltage multiplexing circuits require pre-charging of the output line and switching the pre-charged line to multiple logic levels corresponding to binary input states. Such a system is described in an article by Singh entitled "Four Valued Buses for Clocked CMOS VLSI Systems" published by the IEEE in 1987. The time required to precharge the output line reduces the encoding time period and thus the multiplexing speed of the conventional voltage multiplexing circuit.
The lack of speed of conventional voltage multiplexing methods allows only a limited number of bits of data to be transmitted and received on a single I/O pin. However, with recent increases in device density within an integrated circuit (IC), there is a need for greater number of bits of data to be multiplexed within a given time cycle. One of the major limitations of VLSI IC technology is the limited availability of I/O signal pads. I/O pad density on a VLSI IC or chip is directly proportional to the chip's peripheral dimensions. Although device density has increased drastically in recent years, I/O pad density has remained relatively constant. This causes most large scale digital designs to be I/O-constrained. Typically, a much larger number of I/O pads than are available are needed to effectively utilize the increased gate density. In order to effectively utilize the increase in device density, it is imperative that multiplexing schemes use the limited number of I/O pads to transmit as many binary bits of data as possible.
The actual data transmission rate for a given I/O pin depends on the number of discrete, non-binary encoded voltage levels and the delays incurred in the encoding/decoding process. Thus, faster encoding/decoding circuitry is required to reduce the effects of the I/O bottleneck.